1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to methods and apparatus for controlling the behavior of multiple processors in a distributed computing system.
2. Description of the Related Art
Explosive growth in data center construction has fueled a need for energy consumption awareness, both from the perspective of server power and data center cooling power. Modern servers routinely contain multiple processors and data centers scores or hundreds of servers. Spread out over hundreds of servers, processor power consumption can be enormous. Large numbers of servers and processors dissipate heat and require significant amounts of chilled air to both avoid thermal performance or shutdown issues and to operate at more electrically efficient temperatures. The power consumed by servers directly affects the power required by auxiliary equipment and cooling. Thus, server power conservation translates into overall data center power savings.
Central processing units (CPUs) are organized as nodes with multiple nodes combined into a cluster. One existing solution to increase power consumption efficient utilizes a local algorithm(s) that attempts to maximize power efficiency utilizing information from the processing node. These solutions that rely solely on the local governor provided by the CPU vendor are consequently local to a node and not necessarily related to the cluster workload.
Another prior solution utilizes heterogeneous clusters composed of processors having distinct power and performance characteristics. These approaches use rough heuristics to direct workloads to the processors with the expected best match. Such approaches are static in nature, since the cluster configuration is static, and do not take dynamic workload execution characteristics into consideration. Other previous solutions override the local CPU governor and control the power states globally. Due to the global nature, these solutions are less likely to be able to react quickly to local changes in the power demands.
Modern processors feature Dynamic Voltage and Frequency Scaling (DVFS). Power-aware optimizations make use of this feature to trade-off power and performance. Each voltage and frequency operating point represents a power-saving state of the processor. There are multiple levels of power conservation, the deeper the state the higher the savings, though with an increasing time penalty for state switching. Such processors are equipped with the aforementioned local governors that react to microarchitectural utilization parameters and control processor power states. Such governors are able to react quickly to changing architectural demands, however the decision process is made utilizing only local information.
Another prior solution involves asymmetric clusters consisting of nodes of varying computation capabilities, and corresponding power envelopes. One cluster is composed of power-efficient and lower-performance Atom processors, and more high-performance (and power-hungry) Sandy Bridge processors. This technique utilizes a heuristic to classify each task as either CPU-bound or I/O-bound. CPU-bound tasks are scheduled to high-performance (and thus higher power consumption) processors, whereas I/O tasks are scheduled to the lower-performance (lower power consumption) nodes.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.